FM Receiver muting range setting circuit

ABSTRACT

A muting range setting circuit for an FM receiver uses a pair of differential amplifiers. Each of the differential amplifiers employs the same transistors having like polarity with common input and output terminals. The output of the tuner AFC is compared with an input reference voltage in the differential amplifier circuit and the output representing the frequency deviation of the FM detecting circuit is applied to the gate driving circuit for control of the muting operation.

BACKGROUND OF THE INVENTION

This invention relates to a muting circuit for an FM receiver for relieving adjacent-channel interference produced by local noises during channel selection. More particularly, it relates to a muting range setting circuit in the muting circuit for setting a muting range in which a muting operation is effectuated.

FIG. 1 shows a block diagram illustrating one example of a normally used muting circuit with accompanying circuits. In that Figure, an FM detecting circuit 1 is shown having a function to be described later. Although an antenna, a front end section, an intermediate frequency amplifier (hereinafter referred to merely as IF amplifier when applicable) and the like are not represented in FIG. 1, in an FM receiver, an FM signal received by the antenna is applied to the front end section where it is tuned to a particular broadcast frequency which is in turn converted into an intermediate frequency signal (hereinafter referred to merely as an IF signal when applicable) of 10.7 MHz. These are all standard components to such tuner sections.

This IF signal is applied to the FM detecting circuit 1 through the IF amplifier. In the situation when the input signal of the FM detecting circuit 1, which is delivered from the IF amplifier, deviates from the intermediate frequency of 10.7 MHz, the D.C. output signal of the FM detecting circuit 1 varies in response to the frequency deviation therefrom. The D.C. output signal is a so-called "S curve voltage signal". This output is fed through an AFC circuit 2 to a muting range setting circuit 4 where a muting range in which a muting operation is accomplished, is set. The output of the muting range setting circuit 4 is fed to a gate driving circuit 5. This constitutes a muting driving circuit together with the AFC circuit 2, the muting range setting circuit 4 and a gate circuit 7, to control the operation of a low-frequency amplifier 3. In addition, a D.C. reference voltage source 6 constitutes a part of the muting circuit together with the above described muting driving circuit.

In the muting circuit of the conventional FM receiver, a muting range setting circuit comprises NPN transistors and PNP transistors. In many situations, both the NPN transistors and the PNP transistors are integrated on a common substrate. As a result of this manufacturing step, transistors provided at one side of the substrate are formed as a lateral structure, thereby resulting in decreasing of current amplification factor in each transistor.

Generally, the current amplification factor in a PNP transistor becomes lower than that in the NPN transistor which is formed on the substrate as a planar structure. In order to improve the current amplification factor, it has been proposed to form the PNP and NPN transistors as a composite transistor on the substrate. This composite transistor can be obtained by connecting the transistors in Darlington arrangement. In this case, however, there is a possibility that the muting range may be set unsymmetrically with respect to the intermediate frequency of 10.7 MHz due to the difference in current amplification factor. Furthermore, since the outputs of the respective NPN and PNP transistors have opposite polarities to each other, the conventional muting range setting circuit is disadvantageous in that it is necessary to deliver the outputs of the respective transistors to the gate driving circuit independently. As a result, the circuit becomes overly complicated in construction.

SUMMARY OF THE INVENTION

Accordingly, an object of the present invention is to eliminate the above drawbacks by providing an improved muting range setting circuit for an FM receiver wherein a pair of differential amplifiers which are composed of the same transistors in their polarities, have common input and output terminals.

It is another object of the present invention to provide for a simple muting range setting circuit that is highly reliable and easily fabricated.

These and other objects of the present invention will be described with respect to the preferred embodiment that follows.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings:

FIG. 1 is a block diagram showing one example of a conventional muting circuit for an FM receiver with accompanying circuits;

FIG. 2 is a schematic circuit diagram showing one example of a muting range setting circuit according to this invention; and

FIG. 3 is a graphical representation for a description of an operation of the present muting range setting circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

One preffered example of the present muting range setting circuit will be described with reference to FIGS. 2 and 3.

In FIG. 2, there is shown a muting range setting circuit 4 and a part of a well known muting driving circuit corresponding to a gate driving circuit 5 and a D.C. reference voltage source 6 as shown in FIG. 1. The muting range setting circuit 4 comprises a first differential amplifier comprising NPN transistors TR₃ and TR₄ and a resistor R₂ and a second differential amplifier comprising NPN transistors TR₅ and TR₆ and a resistor R₃. Constant current sources 11 and 12 and a load resistor R₁ are coupled as shown. NPN transistors TR₃ and TR₄ have their emitters connected to each other through the resistor R₂, and NPN transistors TR₅ and TR₆ have their emitters connected to each other through the resistor R₃. The constant current sources 11 and 12 are connected to the junctions between the emitter of transistor TR₄ and the resistor R₂ and between the emitter of transistor TR₆ and the resistor R₃, respectively. The bases of transistors TR₄ and TR₅ are connected to the reference D.C. power source 6 in common and the common reference D.C. power source 6 is maintained at a common reference voltage E₁. The collectors of transistors TR₃ and TR₅ are connected to a common output terminal 13 of the both the first and the second differential amplifiers. The output terminal 13 is connected through the load resistor R₁ to a terminal 10 to which a collector power source is supplied. The bases of transistors TR₃ and TR₆ are connected to a common input terminal 8 of both the first and the second differential amplifiers. In addition, the collectors of transistors TR₄ and TR₆ are connected in common to the terminal 10.

The output terminal 13 is connected to the base of a PNP transistor TR₂ in the gate driving circuit 5. The collector of transistor TR₂ is connected to the base of an NPN transistor TR₁, whereas the emitter of the transistor TR₂ is connected to terminal 10 together with the collector of NPN transistor TR₁. The emitter of transistor TR₁ is grounded through resistors R₄ and R₅.

In operation, the output of an AFC circuit 2 shown in FIG. 1 is applied to the common input terminal 8. As shown in FIG. 3, this output of the AFC circuit 2 exhibits an S curve voltage variation in accordance with frequency deviation with respect to an intermediate frequency f₀ of 10.7 MHz. The output voltage of the AFC circuit corresponding to the intermediate frequency f₀ is equal to a reference voltage E₁ which is applied to both bases of transistors TR₄ and TR₅ by a D.C. reference power source, 6.

In this case, since the base voltages of the transistors TR₃ through TR₆ are equal to each other, in the differential amplifiers currents flow through the transistors TR₄ and TR₆ the emitters of which are directly connected to the constant current source 11 and 12, respectively. Accordingly, no outputfrom the differential amplifiers will appear at the output terminal 13.

In the case when the output frequency of an FM detecting circuit 1 shown in FIG. 1 deviates from the intermediate frequency f₀ toward a frequency range higher than the intermediate frequency f₀, the output voltage of the AFC circuit 2 corresponding to the higher frequency, higher than the reference voltage E₁ from source 6, is applied to the common input terminal 8. As a result, the base voltage of the transistor TR₃ becomes higher than that of the transistor TR₄. Accordingly, current also flows through the transistor TR₃.

By contrast, in the case when the output frequency of the FM detecting circuit 1 deviates from the intermediate frequency f₀ toward a frequency range lower than the intermediate frequency f₀, the output voltage of the AFC circuit 2 corresponding to the lower frequency, lower than the reference voltage E₁, is applied to the common input terminal 8. As a result, the base voltage of the transistor TR₅ is higher than that of the transistor TR₆. Accordingly, current also flows through the transistor TR₅. The above mentioned current value is dependent on the respective resistance values of the load resistor R₁, the resistors R₂ and R₃, and the respective current values of the constant current sources 11 and 12. The output corresponding to the D.C. voltage of the AFC circuit which is representative of the frequency deviation of the FM detection circuit 1, appears at the output terminal 13. When the constant current sources 11 and 12 are equal in current value to each other, under an assumption that the resistance value of the load resistors R₁ is R.sub. 1 ', the resistance value of the resistor R₂ is R₂ ' and the resistance value of the resistor R₃ is R₃ ', as the values defined by R₁ '/R₂ ' and R₁ '/R₃ ' increase, the amplification of the difference between the output voltage of the AFC circuit 2 applied to the input terminal 8 and the reference voltage E₁ can be increased.

This output from the output terminal 13 is applied to the base of the transistor TR₂ in the gate driving circuit 5, so that when the output reaches a threshold voltage level, the transistor TR₂ is rendered conductive to start a muting operation.

The transistor TR₁ is rendered conductive when the transistor TR₂ is put in an operative state, and then an output voltage E₂ divided by resistors R₄ and R₅ appears at an output terminal 9. The output voltage E₂ is applied to the gate circuit 7 shown in FIG. 1, so that the gate circuit 7 could control the operation of the low-frequency circuit 3 in response to the output voltage E₂.

Accordingly, it is clear that the threshold levels +Δf and -Δf can be attained by selecting the values of R₁ '/R₂ ' and R₁ '/R₃ ', so that they define muting ranges as indicated by hatched portions in FIG. 3 and define a band pass range. The differential amplifiers should be equal to each other in their characteristics in order to make the absolute values of +Δf and -Δf equal to each other. But since the transistors employed in the present invention are almost equal in their current amplification factor to each other, the resistance values R₁ ' and R₃ ' become almost equal to each other in their resistance.

Furthermore, in the case where only the resistance values R₂ ' and R₃ ' of the resistors R₂ and R₃ are decreased to thereby excessively increase the values of R₁ '/R₂ ' and R_(1'/R) ₃ ', the absolute values of the frequency deviations +Δf and -Δf become excessively small. As a result, there is a possibility that undesired muting operation may occur in the vicinity of the intermediate frequency. On the contrary, in case of decrease in the resistance values R₂ ' and R₃ ' together with R₁ 40 , it may be possible to make the resistance values R₂ ' and R₃ nearly zero. Therefore, the noise signal in the frequency ranges more than +Δf or less than -Δf are positively eliminated.

As is apparent from the above description, the muting range setting circuit 4 of the present invention comprises four transistors equal in polarity to each other. Accordingly, where the muting range setting circuit is produced as an integrated circuit, it is possible to form the transistors as the planar structure with simple manufacturing steps. As a result, the difference in current amplification factor and threshold voltage level across the base and the emitter of a transistor among the respective transistors contained in the muting range setting circuit can be eliminated. In addition, it is unnecessary to take the inherent difference between an NPN transistor and a PNP transistor such as switching speed into consideration.

According to the present invention, there is no need to provide a complicated circuit including composite transistors. It is possible to eliminate drawbacks accompanying conventional muting range setting circuits such as a muting range set unsymmetrically with respect to the intermediate frequency f₀ due to difference in absolute values of frequency deviations +Δf and -Δf from the intermediate frequency f₀.

It is apparent that other modifications and variations of this invention are possible without departing from the essential scope of the invention. 

What is claimed is:
 1. In a muting range setting circuit for an FM receiver having an FM detecting circuit and an AFC circuit providing an input to said muting range setting circuit, said setting circuit delivering an output to a gate driving circuit to define and accomplish signal muting operation within a frequency range, the improvement comprising: a pair of differential amplifiers having common input and output terminals in the same polarity and means to establish a reference voltage for said pair of differential amplifiers, wherein the output of said AFC circuit is compared to said reference voltage and said setting circuit delivering an output indicative of the frequency deviation of said FM detecting circuit to selectively initiate muting operation.
 2. The muting range setting circuit of claim 1, wherein each differential amplifier comprises a pair of NPN transistors.
 3. The muting range setting circuit of claim 2, wherein said means to establish a reference voltage comprises a D.C. source coupled to the bases of the first of each transistor in said pair of transistors.
 4. The muting range setting circuit of claims 2 or 3, wherein the emitters of the first and second transistors in each pair are coupled to each other through a resistor, and wherein the collector of the first transistor in one of said pairs and the collector of the second transistor in the other pair is coupled to a common output terminal.
 5. The muting range setting circuit of claim 4, wherein the input from said AFC circuit is coupled to the bases of the second transistors in each pair.
 6. The muting range setting circuit of claim 5, wherein said circuit is formed as an integrated circuit.
 7. The muting range setting circuit of claims 1, 2 or 3, wherein said circuit is formed as an integrated circuit. 